Fault tolerant architectures for efficient realization of common DSP kernels

Author

Jenkins, W. Kenneth ; Schnaufer, Bemard A.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1992

Firstpage

1320

Abstract

The authors propose combining traditional fault tolerant computer concepts with the inherent modularity of residue number system (RNS) arithmetic to provide failure resistance in high speed digital signal processing (DSP) systems. Triple modular redundancy and quadruple modular redundancy, both of which are used in commercial fault tolerant computers are combined with RNS modularity for realizing important DSP computational kernels. The combination of system level modularity and arithmetic level modularity offers a great deal of flexibility in designing efficient fault tolerant DSP kernels

Keywords

digital arithmetic; fault tolerant computing; redundancy; signal processing; DSP computational kernels; RNS arithmetic; RNS modularity; arithmetic level modularity; digital signal processing; fault tolerant DSP kernels; fault tolerant architectures; fault tolerant computer; high-speed DSP systems; quadruple modular redundancy; residue number system; system level modularity; triple modular redundancy; Arithmetic; Circuit testing; Digital signal processing; Error correction; Fault detection; Fault tolerance; Fault tolerant systems; Hardware; Kernel; Redundancy;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Conference_Location

Washington, DC

Print_ISBN

0-7803-0510-8

Type

conf

DOI

10.1109/MWSCAS.1992.271097

Filename

271097