A novel channel-width estimation technique for VLSI routing

A novel channel-width estimation technique is described which is useful in VLSI routing. VLSI routing is carried out in two stages: global routing followed by detailed routing. Detailed routing is usually performed using a channel-order graph which determines the order in which channels can be routed. The channel width estimation technique was developed so that the channel order graph could be eliminated, to have channels which could be routed independently of each other. The main aim of doing this was to allow parallel processing of channels to speed up the routing process. However, the technique has been found to be useful in optimizing the overall layout of a VLSI chip. The authors describe the channel-width estimation technique and present results to show that using the technique does not degrade the layout produced