A VLSI implementation of an interface for a dual protocol high speed active bus

Author

Ng, Sheau ; Peursem, J.V. ; Hassoun, Marwan ; Davis, James ; Pohm, Arthur

Author_Institution

Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA

fYear

1992

Firstpage

1077

Abstract

A new multiple bus architecture with an active backplane has been developed. The authors examine the existing data transfer protocol for part of the architecture, then develop the complete data transfer protocol for the whole architecture. They also prove the feasibility of bridging a system using this new bus-based architecture to an existing system which uses a different communication network. As an example of this capability, an implementation of a bridge chip for the AN/AYK-14(V) military airborne computer system bus is described

Keywords

VLSI; multiprocessor interconnection networks; protocols; system buses; VLSI implementation; active backplane; bridge chip; bus-based architecture; data transfer protocol; dual protocol high speed active bus; interface; military airborne computer system bus; multiple bus architecture; Backplanes; Bridge circuits; CMOS technology; Computer architecture; Connectors; Control systems; Multiprocessing systems; Protocols; Synchronization; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Conference_Location

Washington, DC

Print_ISBN

0-7803-0510-8

Type

conf

DOI

10.1109/MWSCAS.1992.271107

Filename

271107