Title :
Enhancement in electrical via-yield of porous low-k/Cu integration by reducing CMP pressure
Author :
Tokitoh, S. ; Kondo, S. ; Yoon, B.U. ; Namiki, A. ; Inukai, K. ; Misawa, K. ; Sone, S. ; Shin, H.J. ; Matsubara, Y. ; Ohashi, N. ; Kobayashi, N.
Author_Institution :
Semicond. Leading Edge Technol., Inc., Onogawa, Japan
Abstract :
The effects of CMP pressure on the via resistance yield of dual- and single-damascene interconnects consisting of porous low-k films have been investigated. Porous low-k films with different mechanical strengths (Young´s modulus and hardness) were used. The via resistance yield was found to strongly depend on both the CMP pressure of the via-layer and mechanical strength of the via low-k film. Analysis of the results considering the mechanical and chemical aspects of the CMP process showed that using low-pressure CMP (1.5 psi) resulted in excellent electrical properties for Cu interconnects composed of the porous low-k (k=2.3) film with high mechanical strength (E=9.8GPa, H=1.2GPa).
Keywords :
Young´s modulus; chemical mechanical polishing; copper; dielectric thin films; hardness; integrated circuit interconnections; pressure control; CMP pressure reduction; Cu; Cu interconnects; Young´s modulus; dual-damascene interconnects; electrical via-yield enhancement; hardness; mechanical strength; porous low-k films; porous low-k-Cu integration; single-damascene interconnects; via low-k film; via resistance yield; via-layer; Adhesives; Chemicals; Degradation; Delamination; Dielectric materials; Electric resistance; Lead compounds; Mechanical factors; Parasitic capacitance; Semiconductor films;
Conference_Titel :
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International
Print_ISBN :
0-7803-8308-7
DOI :
10.1109/IITC.2004.1345716
