A VLSI arithmetic unit for a signal processing neural network

The design of a VLSI arithmetic unit for the support of signal processing and neural network algorithms is discussed. The arithmetic unit is conceived to allow the execution of inner product operations maintaining the silicon area and development costs under reasonable limits, and allowing the parameterization of the design in a modular way. A serial-bit pipeline multiplier and a fixed-point number format have been successfully used. These aspects are justified by a study on the accuracy required when implementing certain signal processing and neural network algorithms, for which some numerical examples are given. A design of a whole chip incorporating such an arithmetic unit and the structure of the required control unit are outlined