Interconnection minimization in multiport memories based data path synthesis

The authors present an efficient technique for minimization of interconnect in multiport memory based data path synthesis for application-specific designs. The minimization problem has been formulated as a 0-1 integer linear programming problem. A 0-1 integer linear programming model is presented which performs functional unit and connection allocation tasks simultaneously assuming that registers have already been grouped into multiport memories. Experimental results have shown that the interconnections can be reduced by using this technique