Title :
A high density Twin-Gate OTP cell in pure 28nm CMOS process
Author :
Woan Yun Hsiao ; Chin Yu Mei ; Wen Chao Shen ; Tzong Sheng Chang ; Yue Der Chih ; Ya-Chin King ; Chrong Jung Lin
Author_Institution :
Inst. of Electron. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
Abstract :
A high density high-k gate dielectric breakdown OTP cell with a self-aligned twin-gate isolation in pure 28nm HKMG process is demonstrated. With a merged spacer isolation formed by two tiny metal gates, the OTP cells can be well isolated with an ultra small cell size of 0.0441μm2 in pure 28nm CMOS logic process. The Twin-Gate OTP memory adopts low voltage high-k dielectric breakdown mechanism to obtain 104 times of On/Off ratio by a low program voltage of 4V in 20μs. A tiny and excellent Twin-Gate isolation with wide program and temperature margins has been successfully achieved in this OTP cell. Superior disturbs immunity and data retention further support the new logic OTP cell to be a promising solution in advanced logic NVM applications.
Keywords :
CMOS logic circuits; electric breakdown; high-k dielectric thin films; low-power electronics; CMOS logic process; CMOS process; HKMG process; advanced logic NVM applications; data retention; high density high-k gate dielectric breakdown OTP cell; high density twin-gate OTP cell; logic OTP cell; low voltage high-k dielectric breakdown mechanism; on-off ratio; one-time programmable memories; self-aligned twin-gate isolation; size 28 nm; spacer isolation; temperature margins; time 20 mus; tiny metal gates; twin-gate OTP memory; twin-gate isolation; voltage 4 V; Abstracts; CMOS integrated circuits; CMOS technology; Electric breakdown; Logic gates; Reliability; Stress;
Conference_Titel :
VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program - 2014 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-TSA.2014.6839664
