Characteristics of MOSFET with non-overlapped source-drain to gate region

Author

Lee, Hyunjin ; Chang, Sung-il ; Lee, Jongho ; Shin, Hyungcheol

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea

Volume

2

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

439

Abstract

A MOSFET structure with non-overlapped source-drain to gate region was proposed to overcome the challenges in sub-0.1 μm CMOS device. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. Electrons were induced reasonably under the spacer. Internal physics and speed characteristics were studied with the non-overlap distance. The proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure.

Keywords

MOSFET; inversion layers; 0.1 micron; CMOS device; DIBL characteristics; MOSFET; dielectric spacer; electron concentration; fringing gate electric field; inversion layer; nonoverlapped source-drain to gate region; numerical simulation; source/drain extension; subthreshold slope; Capacitance; Degradation; Delay; Dielectric constant; Electrons; Energy barrier; MOSFET circuits; Physics; Rain;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2002. MIEL 2002. 23rd International Conference on

Print_ISBN

0-7803-7235-2

Type

conf

DOI

10.1109/MIEL.2002.1003293

Filename

1003293