Title :
A 113mm2 32Gb 3b/cell NAND flash memory
Author :
Futatsuyama, Takuya ; Fujita, Norihiro ; Tokiwa, Naoya ; Shindo, Yoshihiko ; Edahiro, Toshiaki ; Kamei, Teruhiko ; Nasu, Hiroaki ; Iwai, Makoto ; Kato, Koji ; Fukuda, Yasuyuki ; Kanagawa, Naoaki ; Abiko, Naofumi ; Matsumoto, Masahide ; Himeno, Toshihiko ;
Author_Institution :
Toshiba, Yokohama, Japan
Abstract :
NAND flash memories are used in digital still cameras, cellular phones, MP3 players and various memory cards. As seen in the growing needs for applications such as solid-state drives and video camcoders, the market demands for larger-capacity storage has continuously increased and NAND flash memories are enabling a wide range of new applications. In such situations, to achieve larger capacity at low cost per bit, technical improvement in feature-size scaling, multi-bit per cell and area reduction are essential. To respond to such continuous requirements of cost reduction and density increase, 32 Gb 3 b/cell (D3) NAND flash memory with sub-35 nm CMOS process is developed. Introduction of sub-35 nm CMOS process and D3 technology doubles the capacity at almost the same chip area compared to previously published 43 nm 16 Gb 2 b/cell (D2) chip and about 80% chip area compared to previously published 56 nm 16 Gb D3 chip. The chip of size 9.215 x 12.247 mm2 = 112.86 mm2 enables the 32 Gb chip to fit in a microSD memory card. The chip architecture has 2 planes with 1.4 K blocks/plane, 1.5 MB block size and 8 KB page size. The block consists of 66 wordlines (WLs) containing 2 dummy WLs between select gates (SGs). All memory cells on the same WL have 3 pages and can be programmed and read simultaneously.
Keywords :
CMOS memory circuits; NAND circuits; flash memories; D3 technology; NAND flash memory; area reduction; feature-size scaling; microSD memory card; multi-bit per cell; storage capacity 32 Gbit; sub-35 nm CMOS process; CMOS technology; Circuits; Control systems; Decoding; Feedback; Flash memory; MOS devices; Manufacturing; Power system reliability; Voltage;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977398