Title :
Improved multi-level control of RRAM using pulse-train programming
Author :
Liang Zhao ; Hong-Yu Chen ; Shih-Chieh Wu ; Zizhen Jiang ; Yu Shimeng ; Tuo-Hung Hou ; Wong, H.-S Philip ; Nishi, Yoshio
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.
Keywords :
integrated circuit reliability; random-access storage; MLC capability; RRAM device; filamentary switching mechanisms; improved multilevel control; multilevel cell capability; pulse-train programming scheme; resistance distribution uniformity; uniform MLC controls;
Conference_Titel :
VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program - 2014 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-TSA.2014.6839673
