Title :
Evaluating `A+B=K´ conditions in constant time
Author :
Cortadella, J. ; Llaberi, J.M.
Author_Institution :
Dept. d´´Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
The authors consider a type of condition that can be evaluated without requiring a complete ALU (arithmetic logic unit) operation. The circuit that is presented detects the condition A+B= K (n-bit numbers) in constant time, avoiding the carry propagation delay. This circuit can be used to detect a wide spectrum of conditions in branch instructions. It can improve the processor performance by advancing the evaluation of conditions and eliminating the pipeline delays produced by these operations
Keywords :
digital arithmetic; branch instructions; conditions; constant time; digital arithmetic; pipeline delays; processor performance; Adders; Arithmetic; Circuits; Concurrent computing; Costs; Performance evaluation; Propagation delay; Tin; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.14912
