Author :
Wei, J.-M. ; Chen, C.-N. ; Chen, K.-T. ; Kuo, C.-F. ; Ong, B.-H. ; Lu, C.-H. ; Liu, C.-C. ; Chiou, H.-C. ; Yeh, H.-C. ; Shieh, J.-H. ; Huang, K.-S. ; Li, K.-I. ; Wu, M.-J. ; Li, M.-H. ; Chou, S.-H. ; Chew, S.-L. ; Lien, W.-L. ; Yau, W.-G. ; Ge, W.-Z. ; La
Abstract :
A low-power and high-performance RFCMOS SoC GPS receiver is introduced in this paper. It is fabricated in a 0.11 mum process with 6.2times6.2mmz TFBGA package. The power consumption is 34 mW during tracking stage and 45 mW during acquisition stage. The tracking sensitivity is up to -165 dBm with the most competitive TTFF performance. This GPS receiver is designed for PND/GSM/CDMA handsets and is compatible with various reference clock frequencies from 12.6 MHz to 40 MHz. It is a highly integrated solution with intelligent power management scheme and minimum external components. The RF performance is not affected by digital activities due to well-designed isolation schemes. The RF and system performance comparison and the chip micrograph is also illustrated.
Keywords :
CMOS digital integrated circuits; Global Positioning System; low-power electronics; radiofrequency integrated circuits; switching circuits; system-on-chip; GPS receiver; PND-GSM-CDMA handsets; RFCMOS GPS SoC; baseband architecture; correlation efficiency; frequency 12.6 MHz to 40 MHz; frequency 1575.42 MHz; intelligent power management scheme; lowest power consumption; power 34 mW; power 45 mW; power switching circuit; reference clock frequencies; size 110 nm; system-on-chip; tracking sensitivity; Clocks; Energy consumption; Energy management; GSM; Global Positioning System; Multiaccess communication; Packaging; Power system management; Radio frequency; Telephone sets;
