Dielectric defects controlling instability in InGaAs n-MOSFETs with Al2O3/ZrO2 gate stack

Author

Deora, S. ; Bersuker, Gennadi ; Loh, W.-Y. ; Matthews, K. ; Hobbs, Chris ; Kirsch, P.D.

Author_Institution

Front End Process, SEMATECH, Albany, NY, USA

fYear

2014

fDate

28-30 April 2014

Firstpage

1

Lastpage

2

Abstract

Instability under positive bias stress (DC and AC) in InGaAs channel nMOSFETs with a a 1nmAl₂O₃/5nmZrO₂ gate stack is studied. It is determined that the threshold voltage shift (ΔV_T) during stress is primarily caused by a recoverable electron trapping at pre-existing defects, which are located pre-dominantly in the Al₂O₃ interfacial layer (IL). Generation of new electron trapping defects is found to occur in the IL, in the region close to the substrate, while trap generation in the high-k dielectric is negligible. The ΔV_T recovery impacts the degradation dependency on the stress duty cycle and frequency.

Keywords

III-V semiconductors; MOSFET; alumina; electron traps; gallium arsenide; high-k dielectric thin films; indium compounds; stress analysis; zirconium compounds; Al₂O₃-ZrO₂; IL; InGaAs; degradation dependency; dielectric defects; electron trapping defects; gate stack; high-k dielectric; instability control; interfacial layer; n-MOSFET channel; positive bias stress; size 1 nm; size 5 nm; stress duty cycle; threshold voltage shift; trap generation; Charge carrier processes; Degradation; Dielectrics; Indium gallium arsenide; Logic gates; Stress; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program - 2014 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-TSA.2014.6839678

Filename

6839678