• DocumentCode
    1617164
  • Title

    BEOL process integration of 65nm Cu/low k interconnects

  • Author

    Jeng, C.C. ; Wan, W.K. ; Lin, H.H. ; Liang, Ming-Shuo ; Tang, K.H. ; Kao, L.C. ; Lo, H.C. ; Chi, K.S. ; Huang, T.C. ; Yao, C.H. ; Lin, C.C. ; Lei, M.D. ; Hsia, Chin C. ; Liang, Mong-Song

  • Author_Institution
    R&D, Adv. Module Technol., Hsin-Chu, Taiwan
  • fYear
    2004
  • Firstpage
    199
  • Lastpage
    201
  • Abstract
    The process development, characterization and performance evaluation of low-k dielectrics to form multi-level Cu interconnects for the 65 nm CMOS technology node are presented. Significant modifications and improvements over 90nm node have been implemented to overcome those challenges as design rules shrink, which include top via corner rounding control for the robust EM/SM reliability, and inline e-beam inspection for via/trench processes optimization. An in-house developed ECP additive "Trameca" for good Cu gap filling and a controllable hump height for good CMP performance are adopted to achieve tight Rs distributions. The facts that 100% yields of 2.1 millions via chain structure and open/short free on 5m long comb/meander structures along with SM/EM meeting the spec all demonstrated the technology to be a highly manufacturable BEOL process for 65 nm technology node.
  • Keywords
    CMOS integrated circuits; copper; dielectric materials; electron beam deposition; etching; integrated circuit interconnections; 65 nm; 90 nm; BEOL process integration; CMOS technology node; CMP performance; Cu; ECP additive; EM reliability; Rs distributions; SM reliability; Trameca; comb structure; gap filling; hump height; inline e-beam inspection; low k interconnects; low-k dielectrics; meander structure; multilevel Cu interconnects; performance evaluation; process development; top via corner rounding control; trench processes; via chain structure; via processes; CMOS technology; Composite materials; Conducting materials; Degradation; Dielectric materials; Etching; Manufacturing industries; Materials testing; Packaging; Semiconductor device manufacture;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International
  • Print_ISBN
    0-7803-8308-7
  • Type

    conf

  • DOI
    10.1109/IITC.2004.1345745
  • Filename
    1345745