Computer-aided synthesis of a bi-dimensional discrete cosine transform chip

The design of an integrated circuit implementing a bidimensional discrete cosine transform (BDCT) is presented. Such a circuit can be used to remove redundancy of video information in low-rate transmission channels and to perform video compression for image storage. The chip architecture is motivated by the fact that the BDCT equations can be solved row-by-row and column-by-column by a simpler monodimensional DCT (MDCT). Therefore, the chip structure is partitioned into three stages: the first and the last one implement MDCTs, while the second stage is a shared memory array. The DCT design was achieved by means of the OLYMPUS synthesis system, an experimental suite of synthesis tools. A parameterized behavioral description of the monodimensional DCT operator was specified in a high-level description language, HardwareC, in terms of concurrent processes communicating through a shared medium. The circuit layer was synthesized automatically from this description