Process optimisation and dual damascene integration of porous CVD SiOC dielectric at 2.4 and 2.2 k-values for 45 nm CMOS technology

Author

Arnal, V. ; Hoofman, R.J.O.M. ; Assous, M. ; Bancken, P.H.L. ; Brokaart, M. ; Brun, P. ; Casanova, N. ; Chapelon, L.L. ; Chevolleau, T. ; Cowache, C. ; Daamen, R. ; Farcy, A. ; Fayolle, M. ; Feldis, H. ; Furukawa, Y. ; Goldberg, C. ; Gosset, L.G. ; Guedj,

Author_Institution

STMicroelectronics, Crolles, France

fYear

2004

Firstpage

202

Lastpage

240

Abstract

Dual damascene integration of porous CVD SiOC low-k material was performed for interconnects of the 65 and 45 nm technology nodes. Deposition processes with dielectric constant of 2.4 and 2.2 were developed and characterized. Low-k integration was performed with feature sizes down to 85 nm. Etch and strip processes compatible with this ultra low-k investigated and lead to the successful dual damascene integration, illustrated by physical and electrical results such as low leakage current, via chain and line resistances. The k-value after integration was preserved at its initial value.

Keywords

CMOS integrated circuits; chemical vapour deposition; dielectric materials; etching; integrated circuit interconnections; optimisation; porous materials; silicon compounds; 45 nm; 65 nm; CMOS technology; SiOC; deposition processes; dielectric constant; dual damascene integration; interconnects; k-value; leakage current; line resistances; low-k material; porous CVD SiOC dielectric; process optimisation; via chain; Breakdown voltage; CMOS process; CMOS technology; Damascene integration; Dielectric materials; Dielectric measurements; Etching; Integrated circuit interconnections; Mechanical factors; Strips;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International

Print_ISBN

0-7803-8308-7

Type

conf

DOI

10.1109/IITC.2004.1345746

Filename

1345746