An 18Gb/s duobinary receiver with a CDR-assisted DFE

In this paper three techniques are developed, namely: (1) a clock-data recovery (CDR)-assisted duobinary-based decision feedback equalizer (DFE) technique in which first tap feedback is eliminated, and clock phase can be accurately recovered even when using multirate clock DFE; (2) a fast dedicated-path feedback technique that achieves less than 2T feedback time for second post tap; and (3) a duobinary-based symbol-rate clock recovery technique in which it is sufficient to only sample at symbol-rate intervals (i.e., double over-sampling is not required) for extracting both data and edge timing. The receiver measurements are performed using a 25 cm low-epsiv board as a channel with 14 dB loss at 9 GHz, and all measurements used 18 Gb/s 2⁷-1 psuedorandom bit sequence (PRBS) pattern. Results show that the symbol-rate CDR-assisted DFE successfully equalizes the received waveform and achieves BER < 10^-12.