Title :
Ultra-thinned chips integration: technological approach and electrical qualification
Author :
Lépinois, F. ; Pinel, S. ; Cazarré, A. ; Tasselli, J. ; Marty, A. ; Bailbé, J.P. ; Morante, J.R. ; Murray, F. ; Gonnard, O.
Author_Institution :
Lab. of Anal. & Architectrue of Syst., Toulouse, France
fDate :
6/24/1905 12:00:00 AM
Abstract :
Development of advanced packaging technologies such as Chip Size Packages, Multi Chip Modules and 3D stacks of MCMs has led to a significant reduction in mass and volume of electronics systems. Among these techniques, we develop a vertical integration called "Ultra-Thin Chip Stacking" interesting for all applications where size and weight reductions are of major importance (portable electronics, biomedical, aerospace...)
Keywords :
integrated circuit interconnections; multichip modules; 3D stacks; Ultra-Thin Chip Stacking; advanced packaging technologies; chip size packages; electrical qualification; mass; multi chip modules; size reductions; ultra-thinned chips integration; vertical integration; volume; weight reductions; Aerospace electronics; Art; Electronics packaging; Glass; Integrated circuit interconnections; Lapping; MOSFETs; Qualifications; Silicon; Stacking;
Conference_Titel :
Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-7235-2
DOI :
10.1109/MIEL.2002.1003311
