Title :
A 43.7mW 96GHz PLL in 65nm CMOS
Author :
Tsai, Kun-Hung ; Liu, Shen-Iuan
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
In this paper, a 96 GHz PLL, implemented in 65 nm CMOS, is presented that target W-band applications. PLL is composed of a VCO, a low-power divider chain with the division ratio of 256, a PFD, a charge pump (CP), and a 2nd-order loop filter (LF). In the VCO design, a symmetric inductor and a cross-coupled pair are adopted to achieve a high oscillation frequency and a low power consumption.For the divider chain, the four different divider topologies are adopted in a descendant order of the frequency.
Keywords :
CMOS integrated circuits; charge pump circuits; field effect MIMIC; integrated circuit design; low-power electronics; millimetre wave filters; millimetre wave oscillators; phase locked loops; power dividers; voltage-controlled oscillators; 2nd-order loop filter; CMOS integrated circuit; VCO design; W-band application; charge pump circuit; frequency 96 GHz; low-power divider chain; phase locked loop; power 43.7 mW; size 65 nm; Frequency conversion; Injection-locked oscillators; Noise measurement; Phase locked loops; Phase measurement; Phase noise; Semiconductor device measurement; Solid state circuits; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-3458-9
DOI :
10.1109/ISSCC.2009.4977415
