DocumentCode :
1617247
Title :
Influence of via liner properties on the current density and resistance of vias
Author :
Reeves, G.K. ; Holland, A.S. ; Leech, P.
Author_Institution :
Fac. of Eng., RMIT Univ., Melbourne, Vic., Australia
Volume :
2
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Firstpage :
535
Lastpage :
538
Abstract :
Reduced dimensional features have resulted in an increase in the resistance and the current density within vias and interconnects. The introduction of copper has partially addressed these problems. However in the case of an interconnect via the liner\´s resistivity is much higher than the via metal via and the presence of a liner can significantly affect the via\´s electrical properties. Thus a 3-dimensional Finite Element analysis of a via model is undertaken in this paper. The influence of the liner resistivity ρL, thickness t and the liner-via metal interface barrier (ρC2) on via resistance Rv and the current density are quantitatively determined for the first time. A number of the results are readily interpreted in terms of a "transfer length" Lt parameter for current flow from the liner sidewalls to the via plug
Keywords :
ULSI; current density; electric resistance; finite element analysis; integrated circuit interconnections; integrated circuit modelling; 3-dimensional finite element analysis; ULSI; current flow; dimensional features; interconnect technology; interconnects; liner resistivity; liner thickness; liner-via metal interface barrier; model accuracy; transfer length; via current density; via liner properties; via resistance; Conductivity; Copper; Current density; Electric resistance; Electrical capacitance tomography; Electromigration; Finite element methods; Metallization; Plugs; Ultra large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-7235-2
Type :
conf
DOI :
10.1109/MIEL.2002.1003314
Filename :
1003314
Link To Document :
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