Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications

Author

Erh-Hao Chen ; Tzu-Chien Hsu ; Cha-Hsin Lin ; Pei-Jer Tzeng ; Chung-Chih Wang ; Shang-Chun Chen ; Jui-Chin Chen ; Chien-Chou Chen ; Yu-Chen Hsin ; Po-Chih Chang ; Yiu-Hsiang Chang ; Shin-Chiang Chen ; Yu-Ming Lin ; Sue-Chen Liao ; Cheng-Ta Ko ; Chau-Jie Z

Author_Institution

Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

2014

fDate

28-30 April 2014

Firstpage

1

Lastpage

2

Abstract

Technologies of fine-pitch backside via last 3DIC through silicon via (TSV) process are developed to be applied to the mass production of 3D IC products. The detailed process development key points and challenges are disclosed. The electrical data are also analyzed to check the TSV process. Also, its application in real 3DIC system is demonstrated to show the benefits of system form factor and frame rate.

Keywords

fine-pitch technology; integrated circuit packaging; three-dimensional integrated circuits; 3D IC products; 3D IC system; 3DIC through silicon via process; TSV; electrical characteristics; electrical data analysis; fine-pitch backside technology; frame rate; mass production; system form factor; Etching; Foundries; Laboratories; Metals; Silicon; Three-dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program - 2014 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-TSA.2014.6839695

Filename

6839695