Efficient hardware implementation of RSA cryptography

This paper presents the design and implementation of a RSA crypto accelerator. The purpose is to present an efficient hardware implementation technique of RSA cryptosystem using standard algorithms and HDL based hardware design methodology. The paper will cover the RSA encryption algorithm, interleaved multiplication, Miller Rabin algorithm for primality test, extended Euclidean math, non restoring division and Verilog HDL based hardware implementation in FPGA device of the proposed RSA calculation architecture. The results of fast implementations of RSA architecture using Xilinx´s Virtex FPGA device are presented and analyzed. Finally, conclusion is drawn, which highlights the advantages of a fully flexible & parameterized design.