Fault-driven testing of LSI analog circuits

Attempts to reduce production testing time by presenting a fault-driven methodology to handle LSI analog circuits. A fault-driven methodology has to be able to detect both parametric and catastrophic faults. For statistical performance simulation to detect parametric faults, a two level approach is proposed because of the high cost of simulating LSI analog circuits statistically, where a set of primary statistical variables is first mapped to block performances by empirical models, derived by statistical regression techniques, and then mapped to system performances using a behavioural simulator. For catastrophic fault simulation, open and short circuits are mapped to distortions in block performances by simulation and then mapped to system performances using a behavioral simulator. Using the statistical simulation technique for parametric variations and the fault simulation technique for catastrophic faults, testing time is minimized using the algorithm described by L. Milor and A. Sangiovanni-Vincentelli (1990) by eliminating unnecessary specification tests and optimizing the order of tests. The effectiveness and fault coverage of block level testing are also investigated