Title :
Edge effect prediction in real MOS insulator using test chips
Author :
Yugami, Jiro ; Hiraiwa, Atsushi
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
Proposes an analytic method of predicting pattern edge enhanced leakage currents in MOS capacitors with arbitrary geometry, based on test chip I-V measurements. The predicted results are in good agreement with experimental results. Using this method, it becomes possible to qualitatively compare the magnitudes of edge effects under different processing conditions. It is concluded that this method will be a powerful tool for developing high-reliability insulators in future LSIs
Keywords :
MOS integrated circuits; circuit reliability; integrated circuit testing; large scale integration; metal-insulator-semiconductor devices; I-V measurements; LSIs; MOS capacitors; MOS insulator; arbitrary geometry; edge effects; high-reliability insulators; pattern edge enhanced leakage currents; test chips; Birds; Current measurement; Electrodes; Geometry; Insulation; Insulator testing; Leakage current; MOS capacitors; Semiconductor device measurement; Voltage;
Conference_Titel :
Microelectronic Test Structures, 1991. ICMTS 1991. Proceedings of the 1991 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
0-87942-588-1
DOI :
10.1109/ICMTS.1990.161706
