Automated ILA design for VLSI synchronous state machines

Author

Liu, M.N. ; Liu, K.Z. ; Maki, G.K. ; Whitaker, S.R.

Author_Institution

NASA Eng. Res. Center for VLSI Syst. Design, Idaho Univ., Moscow, ID, USA

fYear

1992

Firstpage

851

Abstract

An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This architecture realizes a sequential circuit by replicating simple basic modules. With an ILA architecture, a sequential machine can be built into a very regular form automatically generated by a computer program with a single type of ILA module. The simplicity and programmability of the ILA architecture significantly reduce the design task in all stages of VLSI implementation, including logic design, circuit design, artwork generation, and verification. A software algorithm in the C language hs been developed and tested to generate 1-μm CMOS layouts using the Hewlett-Packard FUNGEN module generator shell

Keywords

C language; CMOS integrated circuits; VLSI; logic CAD; logic arrays; sequential circuits; 1 micron; C language; CMOS layouts; Hewlett-Packard FUNGEN module generator shell; ILA architecture; VLSI implementation; VLSI synchronous state machines; artwork generation; circuit design; iterative logic array; logic design; programmability; synchronous sequential circuits; verification; Circuit synthesis; Circuit testing; Computer architecture; Logic arrays; Logic design; Programmable logic arrays; Sequential circuits; Software algorithms; Software testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Conference_Location

Washington, DC

Print_ISBN

0-7803-0510-8

Type

conf

DOI

10.1109/MWSCAS.1992.271150

Filename

271150