DocumentCode
1617511
Title
Integrated electro-chemical mechanical planarization (Ecmp) for future generation device technology
Author
Economikos, L. ; Wang, X. ; Sakamoto, A. ; Ong, P. ; Naujok, M. ; Knarr, R. ; Chen, L. ; Moon, Y. ; Neo, S. ; Salfelder, J. ; Duboust, A. ; Manens, A. ; Lu, W. ; Shrauti, S. ; Liu, F. ; Tsai, S. ; Swart, W.
Author_Institution
IBM Microelectron., White Plains, NY, USA
fYear
2004
Firstpage
233
Lastpage
235
Abstract
A novel copper (Cu) planarization process, Ecmp, integrating electro-chemical mechanical polishing capability on a 300mm CMP platform with low down force conventional polishing processes is being developed and evaluated on low-k CVD devices. In the integrated Ecmp process, the bulk Cu is removed by electro-chemical mechanical polishing at a high rate which is controlled by applied charge and is independent of down force (0.3psi bulk Cu removal step). The Ecmp process removes topography efficiently and produces a thin planarized Cu film across the wafer to match that of the conventional Cu planarization step. The Cu thickness profile produced by electro-chemical planarization allows the conventional planarization process to clear remaining Cu with low dishing across the wafer. Therefore, an excessive dielectric removal for dishing correction is not required, making the process extendible to ultra-low k dielectrics that require a protective capping layer to be retained after polishing. Experiments are conducted to evaluate the planarization efficiency, film profile, and endpoint control, cost of consumables, pattern density sensitivity and defect density. The mechanical and electrical results indicate that Ecmp enables the planarization of dual damascene structures with minimal dielectric erosion and defect density.
Keywords
chemical mechanical polishing; copper; planarisation; semiconductor technology; 300 mm; Cu; copper planarization process; defect density; device technology; dielectric erosion; dielectric removal; dishing correction; dual damascene structures; electro-chemical mechanical planarization; electro-chemical mechanical polishing; endpoint control; film profile; low-k CVD devices; pattern density sensitivity; planarization efficiency; protective capping layer; ultra-low k dielectrics; Cleaning; Copper; Costs; Dielectrics; Fabrication; Manufacturing processes; Planarization; Process control; Protection; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2004. Proceedings of the IEEE 2004 International
Print_ISBN
0-7803-8308-7
Type
conf
DOI
10.1109/IITC.2004.1345759
Filename
1345759
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