Title :
Analysis of non-volatile latch circuits with ferroelectric-gate field effect transistors for low power and low voltage operation
Author :
Yamamoto, S. ; Inoue, S. ; Ishiwara, H.
Author_Institution :
Collaborative Res. Center, Tokyo Inst. of Technol., Yokohama, Japan
fDate :
6/24/1905 12:00:00 AM
Abstract :
A novel circuit configuration of non-volatile latch circuit with ferroelectric-gate field effect transistors is proposed. SPICE analysis of the circuit operation with 1 V power supply is performed and successful data restoring feature is obtained
Keywords :
SPICE; ferroelectric devices; field effect transistor circuits; flip-flops; insulated gate field effect transistors; low-power electronics; 1 V; SPICE analysis; data restoration; ferroelectric gate field effect transistor; low power operation; low voltage operation; nonvolatile latch circuit; CMOS logic circuits; Capacitors; FETs; Ferroelectric materials; Inverters; Latches; Nonvolatile memory; Polarization; Power supplies; Voltage;
Conference_Titel :
Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-7235-2
DOI :
10.1109/MIEL.2002.1003326
