A novel memory controller architecture

In this paper, a novel common memory controller architecture is proposed. This common architecture includes the most major and important features for any manufacturer, these features can be enabled or disabled according to the manufacturer desire. This architecture can be utilized in any application according to desire of the manufacturer. Additionally, this architecture combines the advantages of most widely known protocols on the scene. This proposed architecture combines the most powerful and distinctive features among most famed specifications. In order to accomplish comprehensive and diverse features, we focus on six protocols which are Flex-OneNAND, Open NAND Flash Memory (ONFI), Embedded Multi-Media Card (eMMC), Hybrid Memory Cube (HMC), WideIO, and Universal Flash Storage (UFS). Diversity through these specifications is easily noticeable. First of all, there are intervals between these protocols which show the trend of the future architecture needs. These specifications covered the most important types of memory; FLASH and DRAM in one device. This novel architecture has extremely simple design which can utilize in many applications. The host can handle the power consumption efficiently. Through a comparative study for these protocols, an important key result is reached, although that the industry always looking forward to improve the performance, but the main objective is to reduce the consumed power by the device, Thus the major objective also of this common architecture is to conserve the energy.