Title :
Enhanced delay test generator for high-speed logic LSIs
Author :
Hatayama, Kazumi ; Ikeda, Mitsuji ; Hayashi, Terumine ; Kishida, Kuniaki ; Takakura, Masahiro ; Ishiyama, S.
Author_Institution :
Hitachi Ltd., Ibaraki, Japan
Abstract :
An enhanced delay test generation procedure for high-speed logic LSIs is presented. The procedure is applicable to general scan-designed sequential circuits including both level-type flip-flops and edge-type flip-flops. Some techniques are introduced to solve the problem of `same-clock signal transfer´ between these flip-flops and to enhance the performance of the delay test generation procedure. The effectiveness of the procedure is demonstrated by the experimental results obtained
Keywords :
automatic testing; flip-flops; integrated circuit testing; integrated logic circuits; large scale integration; logic testing; sequential circuits; automatic testing; edge-type flip-flops; effectiveness; enhanced delay test generation; high-speed logic LSIs; level-type flip-flops; same-clock signal transfer; scan-designed sequential circuits; Circuit faults; Circuit testing; Combinational circuits; Delay effects; Large scale integration; Logic circuits; Logic devices; Logic testing; Propagation delay; Test pattern generators;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82290
