A 2.5MS/s 225 µW 8-bit charge redistribution SAR ADC for multichannel applications

Author

Otfinowski, Piotr

Author_Institution

Dept. of Meas. & Instrum., AGH Univ. of Sci. & Technol., Cracow, Poland

fYear

2010

Firstpage

182

Lastpage

185

Abstract

This paper presents a design of integrated analog-to-digital converter implemented in UMC CMOS 180nm technology dedicated to multichannel readout circuits. The successive approximation architecture with charge redistribution was proposed. A capacitive DAC is presented, where CMOS switches are described in detail in terms of speed and accuracy. In order to reduce the DAC´s area, a resistive auxiliary sub-DAC is also presented. A synchronous 30 MHz latch with preamplifier is used as a comparator. Designed ADC achieves conversion rates of 3 MS/s at 225 μW. Final simulation results indicate low nonlinearity of 0.3 LSB of the presented circuit.

Keywords

CMOS integrated circuits; analogue-digital conversion; digital readout; 8-bit charge redistribution SAR ADC; CMOS switches; LSB nonlinearity; UMC CMOS technology; capacitive DAC; comparator; frequency 30 MHz; integrated analog-to-digital converter; multichannel readout circuits; power 225 muW; preamplifier; size 180 nm; successive approximation architecture; Accuracy; Approximation methods; Capacitance; Capacitors; Digital-analog conversion; Logic gates; Transistors; CMOS switch; SAR; analog to digital converter; successive approximation;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings of the 17th International Conference

Conference_Location

Warsaw

Print_ISBN

978-1-4244-7011-2

Electronic_ISBN

978-83-928756-4-2

Type

conf

Filename

5551536