A 0.5 V, 420 MSps, 7-bit flash ADC using all-digital time-domain delay interpolation

Author

Lin, James ; Mano, Ibuki ; Miyahara, Masaya ; Matsuzawa, Akira

Author_Institution

Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2012

Firstpage

1

Lastpage

2

Abstract

This paper presents a 0.5 V ultra-low-voltage flash ADC using an all-digital time-domain delay interpolation technique for resolution enhancement. The developed 7-bit flash ADC is implemented in a 90 nm CMOS process. By using two-way time-interleaving, it achieves an ENOB of 5.5 bits while operating at 420 MSps consuming a total power of 4.1 mW. The measured peak FoM is 195 fJ/conv.-step during single-channel operation at 210 MSps.

Keywords

CMOS integrated circuits; analogue-digital conversion; interpolation; time-domain analysis; CMOS process; ENOB; FoM; all-digital time-domain delay interpolation technique; figure of merit; power 4.1 mW; resolution enhancement; single-channel operation; size 90 nm; two-way time-interleaving; ultra-low-voltage flash ADC; voltage 0.5 V; word length 5.5 bit; word length 7 bit; Calibration; Capacitance; Delays; Interpolation; Latches; Method of moments; Time-domain analysis; delay interpolation; flash ADC; ultra-low-voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on

Conference_Location

Bangkok

Print_ISBN

978-1-4673-5694-7

Type

conf

DOI

10.1109/EDSSC.2012.6482785

Filename

6482785