A 25mA 0.13µm CMOS LDO regulator with power-supply rejection better than −56dB up to 10MHz using a feedforward ripple-cancellation technique

Low drop-out (LDO) linear regulators have become a key building block in portable communication systems for power management ICs. The LDO usually comes after a switching DC-DC converter to reduce the output ripples and provide a regulated voltage source for noise-sensitive blocks. For a higher level of integration, there is a need to increase the operating frequency of the switching converters. This necessitates a subsequent LDO regulator with high ripple rejection at frequencies up to several MHz. These LDO regulators should also provide a low drop-out voltage to cope with the low supply voltage of the state-of-the-art CMOS technology.This paper presents a high PSR low-voltage LDO regulator using a feedforward ripple cancellation (FFRC) technique. The LDO maintains conventional loop dynamics, supplies high current, has a low quiescent current, and provides a PSR better than -56dB over a wide frequency range.