Title :
Algorithmic test generation for supply current testing of TTL combinational circuits
Author :
Kuchii, Toshimasa ; Hashizume, Masaki ; Tamesada, Takeomi
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokushima Univ., Japan
Abstract :
In this paper, an algorithmic test generation method for supply current testing of TTL combinational circuits is proposed. In this method, primary input assignment like in PODEM is used for sensitizing a fault and generating the fault effect on supply current of a circuit under test. Test input vectors for ISCAS-85 benchmark circuits are derived by a random method and the proposed algorithmic method. The test generation results show that with the algorithmic method, test input vectors of faults, whose test vectors can not be derived with the random method, can be derived
Keywords :
automatic testing; bipolar logic circuits; combinational circuits; fault diagnosis; integrated circuit testing; logic testing; transistor-transistor logic; AND gate; ATPG; IDDQ testing; ISCAS-85 benchmark circuits; NAND gate; PODEM; TTL combinational circuits; algorithmic test generation method; bipolar circuit testing; bridging fault; fault vectors; open fault; primary input assignment; random method; supply current testing; test input vectors; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Current measurement; Current supplies; Electrical fault detection; Fault detection; Logic; System testing;
Conference_Titel :
Test Symposium, 1996., Proceedings of the Fifth Asian
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-7478-4
DOI :
10.1109/ATS.1996.555155
