DocumentCode
1618189
Title
Approach to solve the reliability problem at packaging level in the matrix VLSI
Author
Vasiltsov, Igor V. ; Mandziy, Bohdan A. ; Bench, Andriy
Author_Institution
Inst. of Comput. Informational Technol., Temopil Acad. of Nat. Economy, Ukraine
Volume
2
fYear
2002
fDate
6/24/1905 12:00:00 AM
Firstpage
703
Lastpage
706
Abstract
In this paper the problem of increasing the reliability of the designed devices, implemented on the matrix VLSI has been considered. The proposed approach consists in choosing of the special area in the chip during mapping procedure at the packaging level. Usage of such approach allows for the designer to obtain a more optimal topology solution, and thus will increase the reliability of designed devices
Keywords
VLSI; circuit optimisation; integrated circuit design; integrated circuit packaging; integrated circuit reliability; network topology; mapping procedure; matrix VLSI; optimal topology solution; packaging level; reliability problem; Chemical technology; Costs; Military computing; Packaging; Power generation; Power supplies; Power system reliability; Tellurium; Topology; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Conference_Location
Nis
Print_ISBN
0-7803-7235-2
Type
conf
DOI
10.1109/MIEL.2002.1003355
Filename
1003355
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