A 40Gb/s full-rate 2:1 MUX in 0.18µm CMOS

Serial data communication systems operating at throughputs of 40 Gb/s have been developed in recent years to increase transmission capacity. A data multiplexer (MUX) is a key block in any high-speed data communication system. Several 4:1 MUX circuits have been reported in technologies such as SiGe, GaAsand InP at speeds of 40 Gb/s or higher. CMOS implementations of half-rate MUX circuits have been also reported. A full-rate architecture would be desirable in order to reduce the deterministic jitter. This paper describes high-speed design techniques used for retiming of 40 Gb/s data signals and generation of 40 GHz clock signals.