An 80mW 40Gb/s 7-Tap T/2-Spaced FFE in 65nm CMOS

Author

Momtaz, A. ; Green, Michael M.

Author_Institution

Univ. of California, Irvine, CA

fYear

2009

Firstpage

364

Abstract

The ever-increasing demand for higher communication bandwidth is pressuring the industry to produce links with 40 Gb/s data rate. At this data rate, channel dispersion greatly limits the transmission length, making deployment of dispersion compensators a necessity. Due to its fast adaptation speed and ease of integration within the transceiver, electronic dispersion compensation (EDC) is receiving a great deal of attention. An FFE is currently the most practical implementation of EDC for 40 Gb/s data rates, reflecting its advantages as a simple structure with moderate design complexity. Based on system-level simulations of a 40Gb/s SMF link and a T/2-spaced FFE, a 7-tap T/2-spaced FFE is implemented in this work.

Keywords

CMOS integrated circuits; CMOS; SMF link; T-2-spaced FFE; bit rate 40 Gbit/s; channel dispersion; electronic dispersion compensation; power 80 mW; size 65 nm; Bandwidth; Delay; Equalizers; Finite impulse response filter; Inductance; Optical fiber communication; Semiconductor device measurement; Time measurement; Transmission lines; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-3458-9

Type

conf

DOI

10.1109/ISSCC.2009.4977459

Filename

4977459