• DocumentCode
    1618261
  • Title

    A hardware design of MS/MMS-based LDPC decoder

  • Author

    Tanyanon, I. ; Choomchuay, Somsak

  • Author_Institution
    Dept. of Electron. Eng., King Mongkut´s Inst. of Technol. Ladkrabang, Bangkok, Thailand
  • fYear
    2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents a hardware design of a LDPC decoder where Min-Sum (MS) and Modified Min-Sum (MMS) algorithm has been investigated. The parity check matrix is complied with IEEE 802.11n recommendation (code rate of 0.5, 648 bits block length). Verilog description language is employed for Xilinx XC2VP30-7 FPGA. With the matrix reordering technique, the final design shows that the data rate of 127 Mbps could be achieved when the pipeline stages are used.
  • Keywords
    field programmable gate arrays; hardware description languages; matrix algebra; parity check codes; wireless LAN; IEEE 802.11n recommendation; MS/MMS-based LDPC decoder; Verilog description language; Xilinx XC2VP30-7 FPGA; hardware design; matrix reordering technique; modified min-sum algorithm; parity check matrix; Algorithm design and analysis; Computer architecture; Decoding; Field programmable gate arrays; Hardware; Parity check codes; Pipeline processing; LDPC; Overlap; matrix reodering; modified min-sum;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on
  • Conference_Location
    Bangkok
  • Print_ISBN
    978-1-4673-5694-7
  • Type

    conf

  • DOI
    10.1109/EDSSC.2012.6482804
  • Filename
    6482804
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1618261