A new approach for analyzing a digital descriptor regulator with floating point computation

Presents a novel technique for analyzing the performance of a randomly distributed digital descriptor regulator having an analog-to-digital (A/D) converter with finite wordlength and a reduced-order estimator/controller block that is implemented by a floating-point computer with finite mantissa length. The approach is based on transferring the original descriptor system with white noise disturbances into a reduced-order descriptor model which runs completely with known inputs. This model is then composed into slow and fast subsystems, using the Drazin inverse technique, where a new reduced-order controller is obtained. A closed-form upper bound on the mean-square semistate errors of a multivariable descriptor system, where floating-point arithmetic is used in the estimator/controller computation, is derived. This bound can be used to analyze the stability of the unstable modes of the system. The error-performance/hardware-cost tradeoff for wordlength design choice is introduced