A high-resolution CMOS sigma-delta A/D converter with 320 kHz output rate

Author

Rebeschini, Mike ; Van Bavel, Nicholas ; Rakers, Pat ; Greene, Robert ; Caldwell, Jim ; Haug, John

Author_Institution

Motorola Inc., Schaumburg, IL, USA

fYear

1989

Firstpage

246

Abstract

A third-order switched-capacitor sigma-delta A/D converter is presented. The converter consists of three cascaded first-order sigma-delta modulators, and achieves 88 dB pk/rms S/(N+D) in a 160-kHz passband with a 10.24-MHz sampling rate. The high signal-to-noise ratio is maintained over this wide bandwidth by attenuating the quantization noise with a third-order noise-shaping function and a fourth-order comb decimation filter. A special autozeroed integrator with low pole error is required to achieve the 10.24-MHz sampling rate and high-order noise shaping simultaneously

Keywords

CMOS integrated circuits; analogue-digital conversion; switched capacitor networks; 10.24 MHz; 160 kHz; 320 kHz; ADC; CMOS; autozeroed integrator; fourth-order comb decimation filter; high SNR; high-resolution; low pole error; monolithic IC; noise-shaping function; quantisation noise attenuation; sigma-delta A/D converter; sigma-delta modulators; switched-capacitor; third-order; Capacitors; Delta-sigma modulation; Digital filters; Digital modulation; Low pass filters; Noise shaping; Operational amplifiers; Quantization; Sampling methods; Silicon compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100337

Filename

100337