Title :
A low noise CMOS phase locked loop
Author :
Ling, Chaodong ; Luo, Miaoyi ; Cheng, Mengzhang
Author_Institution :
Coll. of Inf. Sci. & Eng., Huaqiao Univ., Quanzhou, China
Abstract :
A 5 V, 0.6 mum CMOS phase locked loop (PLL) is presented. The circuit design of the PLL, which consists of a phase-frequency-detector (PFD), charge-pump (CPP), bias-generator (BG), voltage controlled oscillator (VCO) and differential to single converter (DSC), is introduced and the simulation results are given. The details of design theory and calculation are also described. The PLL is integrated in CMSC 0.6 mum 5 V 2P2M CMOS technology, the simulation results show that the PLL operates within the frequency range between 100 MHz to 500 MHz, and the phase noise are -89 dBc/Hz and -100 dBc/Hz at 100 KHz and 1 MHz offset frequency.
Keywords :
CMOS integrated circuits; UHF integrated circuits; UHF oscillators; VHF oscillators; charge pump circuits; integrated circuit design; integrated circuit noise; phase locked loops; voltage-controlled oscillators; PLL circuit design; bias-generator circuit; charge-pump circuit; differential-to-single converter; frequency 100 MHz to 500 MHz; low-noise CMOS phase locked loop; phase-frequency-detector; size 0.6 mum; voltage 5 V; voltage controlled oscillator; Charge pumps; Clocks; Filters; Frequency conversion; Phase frequency detector; Phase locked loops; Phase noise; Transfer functions; Voltage control; Voltage-controlled oscillators; Bias generator; PLL; phase frequency detector; voltage controlled oscillator;
Conference_Titel :
Anti-counterfeiting, Security, and Identification in Communication, 2009. ASID 2009. 3rd International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-3883-9
Electronic_ISBN :
978-1-4244-3884-6
DOI :
10.1109/ICASID.2009.5276937
