DocumentCode
1618560
Title
A 2.2GHz 7.6mW sub-sampling PLL with −126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS
Author
Gao, Xiang ; Klumperink, Eric A M ; Bohsali, Mounir ; Nauta, Bram
Author_Institution
Univ. of Twente, Enschede
fYear
2009
Firstpage
392
Abstract
This paper presents a 2.2 GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.
Keywords
CMOS integrated circuits; charge pump circuits; jitter; low-power electronics; phase detectors; phase locked loops; phase noise; voltage-controlled oscillators; CMOS; VCO output; charge-pump; frequency 2.2 GHz; frequency divider; jitter; low in-band phase noise; phase-detector; power 7.6 mW; reference clock; size 0.18 mum; subsampling PLL; Capacitors; Clocks; Frequency locked loops; Frequency synthesizers; Jitter; Phase locked loops; Phase noise; Sampling methods; Space vector pulse width modulation; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International
Conference_Location
San Francisco, CA
Print_ISBN
978-1-4244-3458-9
Type
conf
DOI
10.1109/ISSCC.2009.4977473
Filename
4977473
Link To Document