A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation

As data rate of wireline applications increases, clock skew becomes a significant portion of the overall timing margin and directly affects the BER performance. A variable delay line (VCDL) or a DLL is widely used for elastic timing control not only in source-synchronous serial links but also in clock-and-data- recovery systems for further enhancing the BER performance. The conventional analog delay line, however, suffers from PVT variations, and calibrating the analog delay line brings substantial design efforts. For better testability and robust operation, a digitally controlled delay line is preferred. The semi- digital DLL or the all-digital DLL provides more robust delay control, but achieving fine timing resolution such as sub-ps is still challenging due to an algorithmic jitter problem.