• DocumentCode
    1618676
  • Title

    Design of a fully-digital class-D audio power amplifier based on open-loop configuration

  • Author

    Liyu Lin ; Xiaobo Wu ; Jinchen Zhao ; Menglian Zhao

  • Author_Institution
    Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
  • fYear
    2012
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    A fully-digital open-loop class-D audio power amplifier is presented. By using the proposed error feedback structure, the ΔΣ noise shaper reduces the word length of the input signal while maintaining its precision. An optimized compensation algorithm based on 2x interpolation linearization is proposed to improve the total harmonic distortion (THD), as well as to reduce its hardware overhead. The whole system has been implemented in the standard SMIC 0.18μm 1P6M Logic Salicide process. The test results show that the system achieves a maximal SNDR of 82.9dB and a dynamic range of 83.7dB with a power consumption of 0.12mW under a supply voltage of 1.8V, which is suitable for the application of high-fidelity audio systems.
  • Keywords
    audio-frequency amplifiers; interpolation; open loop systems; power amplifiers; sigma-delta modulation; ΔΣ noise shaper; 1P6M logic salicide process; SMIC; error feedback; fully-digital class-D audio power amplifier; interpolation linearization; open-loop configuration; optimized compensation algorithm; power 0.12 mW; size 0.18 mum; total harmonic distortion; voltage 1.8 V; Algorithm design and analysis; Harmonic distortion; Interpolation; Noise; Power amplifiers; Pulse width modulation; class-D amplifier; harmonic distortion; linearization; noise shaper; pulse width modulation (PWM);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on
  • Conference_Location
    Bangkok
  • Print_ISBN
    978-1-4673-5694-7
  • Type

    conf

  • DOI
    10.1109/EDSSC.2012.6482818
  • Filename
    6482818