A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS

The requirements of next-generation wireless terminals are driving RFIC design toward ubiquitous multistandard connectivity at reduced power consumption and cost. While the use of scaled CMOS technology is required to allow economically feasible single-chip integration with a digital processor a software-defined radio (SDR) is the preferred approach to provide a reconfigurable platform, that covers a broad range of noise/linearity specifications while offering the best power/performance trade-off. A 0.1-to-5GHz SDR receiver, including LO generation, has been developed in a 45nm CMOS technology. To be competitive with dedicated single-mode radios, this SDR combines the most demanding requirements such as high sensitivities for cellular standards, low phase noise, and high linearity for the inter-modulation test in DVB-H mode. The presented prototype achieves all these targets by exploiting the speed capabilities of the scaled digital technology while minimizing the total area occupied by passive devices.