Title :
A buffer-based algorithmic analog-to-digital converter
Author :
Ogawa, Satomi ; Kondo, Kazuyuki ; Watanabe, Keno
Author_Institution :
Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan
Abstract :
An algorithmic analog-to-digital (A/D) converter is proposed which uses unity-gain buffers instead of op-amps to perform the analog arithmetic operation. Error analysis shows that a conversion accuracy higher than 8 b is possible with presently available CMOS technologies. The device count is minimum, and thus it is suited for an A/D converter implemented by ASICs. A prototype converter built using discrete components has confirmed the principles of operation
Keywords :
CMOS integrated circuits; analogue-digital conversion; A/D converter; ASICs; CMOS; analog arithmetic operation; conversion accuracy; error analysis; monolithic implementation; unity-gain buffers; Analog-digital conversion; CMOS technology; Clocks; Error analysis; Operational amplifiers; Pipelines; Prototypes; Signal processing algorithms; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100344
