A 1.3-V, 9.1μW wide-dynamic range logarithmic amplifier for cochlear implant system

Author

Sundarasaradula, Yuwadee ; Thanachayanont, Apinunt

Author_Institution

Fac. of Eng., King Mongkut´s Inst. of Technol. Ladkrabang, Bangkok, Thailand

fYear

2014

fDate

14-17 May 2014

Firstpage

1

Lastpage

4

Abstract

This paper presents the design and realization of a low-noise, low-power, wide-dynamic-range CMOS logarithmic amplifier for cochlear implant system in a standard 0.18μm CMOS technology. The proposed logarithmic amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. The overall circuit consumes only 9.1 μW from a 1.3 V single power supply voltage. The simulated input dynamic range is 80 dB, which covers the input amplitudes ranging from 10 μV to 100 mV. The simulated bandwidth of the amplifier is from 50 Hz to 24 kHz. The simulated total input-referred noise is 4.81 μV, integrated from 100 Hz to 10 kHz.

Keywords

CMOS integrated circuits; amplifiers; cochlear implants; power supply circuits; bandwidth 100 Hz to 10 kHz; bandwidth 50 Hz to 24 kHz; cochlear implant system; gain 80 dB; low-noise CMOS logarithmic amplifier; low-powerCMOS logarithmic amplifier; piecewise linear function; power 9.1 muW; power supply voltage; progressive-compression parallel-summation architecture; size 0.18 mum; voltage 1.3 V; voltage 10 muV to 100 mV; voltage 4.812 muV; wide-dynamic-range CMOS logarithmic amplifier; Cochlear implants; Dynamic range; Feedback loop; Gain; Limiting; Noise; Preamplifiers; Cochlear implant; Limiting amplifier; Logarithmic amplifier; subthreshold operation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2014 11th International Conference on

Conference_Location

Nakhon Ratchasima

Type

conf

DOI

10.1109/ECTICon.2014.6839773

Filename

6839773