Clock signal distribution network for high speed testers

Author

Hsue, Ching- Wen

Author_Institution

AT&T Bell Lab., Princeton, NJ, USA

fYear

1989

Firstpage

199

Lastpage

207

Abstract

A high-speed clock distribution network is described. By analyzing the transient behavior of the pulse signal along a multisection transmission line, the author develops a new impedance-matching methodology to reduce the internal multireflection processes due to the impedance discontinuities in the signal line. By means of the bisection method, the matched transmission line is converted into a single-input, 2ⁿ-output, binary-tree distribution circuit. The circuit is realized on a planar printed-circuit board. Experimental results show that this distribution system can provide equiamplitude, high-fidelity, nonskewed signals to all the output terminals for pulse signal frequency in excess of 800 MHz

Keywords

clocks; distributed parameter networks; impedance matching; printed circuits; pulse circuits; test equipment; transients; transmission line theory; 800 MHz; binary-tree distribution circuit; bisection method; equiamplitude; high speed testers; high-speed clock distribution network; impedance discontinuities; impedance-matching; internal multireflection processes; multisection transmission line; nonskewed signals; planar printed-circuit board; pulse signal; transient behavior; Clocks; Distributed parameter circuits; Impedance; Planar transmission lines; Power system transients; Signal analysis; Signal processing; Testing; Transient analysis; Transmission line discontinuities;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/TEST.1989.82295

Filename

82295