Title :
A low power consumption BIST testing technology based on heavy input
Author_Institution :
Coll. of Phys. & Electron. Sci., Guizhou Normal Univ., Guiyang, China
Abstract :
This paper introduces a lower power built-in-self-test technology, which can effectively reduce the average power consumption of under-test circuits during testing. Its basic theory is to improve the structure of test vector generator using ldquoAND/NOrdquo gate tree, therefore decreasing the turn time of ldquoimportant inputrdquo end among under-test circuits to reduce power consumption. The result of Benchmark experiment circuit emulation indicates this method may gain higher test efficiency, and it´s suitable for BIST of digital integrated circuits especially.
Keywords :
built-in self test; digital integrated circuits; integrated circuit testing; logic gates; low-power electronics; AND/NO gate tree; BIST; digital integrated circuit; lower power built-in-self-test technology; power consumption; test vector generator; Built-in self-test; Capacitance; Circuit faults; Circuit testing; Electronic equipment testing; Energy consumption; Integrated circuit technology; Logic testing; Switching circuits; Voltage; Built-in-self-test; Fault coverage Vector leap; Lower power consumption testing; Test pattern generator;
Conference_Titel :
Anti-counterfeiting, Security, and Identification in Communication, 2009. ASID 2009. 3rd International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4244-3883-9
Electronic_ISBN :
978-1-4244-3884-6
DOI :
10.1109/ICASID.2009.5276952
