ESD-transient detection circuit with equivalent capacitance-coupling detection mechanism and high efficiency of layout area in a 65nm CMOS technology

A new power-rail ESD clamp circuit designed with equivalent capacitance-coupling detection mechanism and high efficiency of layout area has been proposed and verified in a 65nm 1.2V CMOS process. The proposed design has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of the proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit by both reducing ~46%.