DocumentCode :
1619325
Title :
Model of asynchronous finite state machines and their pipelined structures
Author :
Shieh, Ming-Der ; Wey, Chin-Long ; Fisher, P. David
Author_Institution :
Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
fYear :
1992
Firstpage :
659
Abstract :
The design of asynchronous finite state machines (AFSMs) has been limited because multiple-input changes are disallowed. A new architecture for designing AFSMs with completion signals, in which the completion signal is generated whenever both outputs and internal states stabilize, is presented. Results show that the proposed design allows multiple-input changes and is free of races and hazards. Based on the proposed architecture, a pipelined AFSM structure is presented
Keywords :
asynchronous sequential logic; logic design; pipeline processing; FSM architecture; FSM design; asynchronous finite state machines; completion signals; multiple-input changes; pipelined structures; Amplitude shift keying; Automata; Clocks; Delay; Hazards; Integrated circuit interconnections; Protocols; Sequential circuits; Signal generators; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0510-8
Type :
conf
DOI :
10.1109/MWSCAS.1992.271237
Filename :
271237
Link To Document :
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